S3C2416X RISC MICROPROCESSOR
WATCHDOG TIMER
2.3 CONSIDERATION OF DEBUGGING ENVIRONMENT
When the S3C2416 is in debug mode using Embedded ICE, the watchdog timer must not operate.
The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal
(DBGACK signal). Once the DBGACK signal in CPU core is asserted, the reset output of the watchdog timer is
not activated as the watchdog timer is expired.
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