Samsung S3C2416 User Manual page 513

S3C2416X RISC MICROPROCESSOR
5.28 CONTROL REGISTER 3
Register
CONTROL3_0 0X4AC00084
CONTROL3_1 0X4A800084
Name Bit
FCSEL3 [31]
FIA3 [30:24] FIFO Interrupt Address register 3
FCSEL2 [23]
FIA2 [22:16] FIFO Interrupt Address register 2
FCSEL1 [15]
FIA1 [14:8]
FCSEL0
FIA0 [6:0]
NOTES:
1. FCSel[3:2] : Tx Feedback Clock Delay Control : Inverter delay means 10ns delay when SDCLK 50MHz setting
01 = Delay1 (basic delay),
00 = Delay3 (inverter delay), 10 = Delay4 (inverter delay + 2ns)
2. FCSel[1:0] : Rx Feedback Clock Delay Control : Inverter delay means10ns delay when SDCLK 50MHz setting
01 = Delay1 (basic delay),
00 = Delay3 (inverter delay), 10 = Delay4 (inverter delay + 2ns)
3. Tx Feedback inversion setting (FCSel[3:2] = 00 or 10), Tx Feedback clock enable (ENFBCLKTX=0) and
Normal Speed mode (ENHIGHSPD = 0) setting make Tx data transfer mismatch (Do not set).
Address R/W
R/W
R/W
Feedback Clock Select [3]
Reference
(note 1)
FIFO (512Byte Buffer memory, word address unit)
Initial value (0x7F) generates at 512-byte (128-word) position.
Feedback Clock Select [2]
Reference
(note 1)
FIFO (512Byte Buffer memory, word address unit)
Initial value (0x5F) generates at 384-byte (96-word) position.
Feedback Clock Select [1]
Reference
(note 2)
FIFO Interrupt Address register 1
FIFO (512Byte Buffer memory, word address unit)
Initial value (0x3F) generates at 256-byte (64-word) position.
[7]
Feedback Clock Select [0]
Reference
(note 2)
FIFO Interrupt Address register 0
FIFO (512Byte Buffer memory, word address unit)
Initial value (0x1F) generates at 128-byte (32-word) position.
11 = Delay2 (basic delay + 2ns),
11 = Delay2 (basic delay + 2ns),
Description
FIFO Interrupt Control (Control Register 3)
(Channel 0)
FIFO Interrupt Control (Control Register 3)
(Channel 1)
Description
HSMMC CONTROLLER
Reset Value
0x7F5F3F1F
0x7F5F3F1F
Initial Value
0x0
0x7F
0x0
0x5F
0x0
0x3F
0x0
0x1F
20-67