Samsung S3C2416 User Manual page 164

NAND FLASH CONTROLLER
10.1.1 1-BIT ECC Register Configuration
Following tables shows the configuration of 1-bit ECC value read from spare area of external NAND flash
memory. For comparing to ECC parity code generated by the H/W modules, each ECC data read from memory
must be written to NFMECCDn for main area and NFSECCD for spare area.
1. NAND Flash Memory Interface
Register
NFMECCD0
NFMECCD1
Register
NFSECCD
7-6
4-bit ECC decoding scheme is different to 1-bit ECC.
Bit [31:24]
nd
Not used
2
th
Not used
4
Bit [31:24]
Not used nd
2
NOTE
Bit [23:16]
ECC for I/O[7:0]
ECC for I/O[7:0]
Bit [23:16]
ECC for I/O[7:0]
S3C2416 RISC MICROPROCESSOR
Bit [15:8]
st
Not used
1
rd
Not used
3
Bit [15:8]
Not used st
1
Bit [7:0]
ECC for I/O[7:0]
ECC for I/O[7:0]
Bit [7:0]
ECC for I/O[7:0]