Data Register Configuration; Steppingstone (8Kb In 64Kb Sram); 1Bit / 4Bit / 8Bit Ecc (Error Correction Code); Ecc Module Features - Samsung S3C2416 User Manual

S3C2416 RISC MICROPROCESSOR

8 DATA REGISTER CONFIGURATION

8.1.1 8-bit NAND Flash Memory Interface
A. Word Access
Register
NFDATA
B. Half-word Access
Register
NFDATA
C. Byte Access
Register
NFDATA

9 STEPPINGSTONE (8KB IN 64KB SRAM)

The NAND Flash controller uses Steppingstone as the buffer on booting and also you can use this area for
various other purpose.

10 1BIT / 4BIT / 8BIT ECC (ERROR CORRECTION CODE)

NAND flash controller has four ECC (Error Correction Code) modules for 1 bit ECC, one for 4bit ECC and one for
8bit ECC.
The 1bit ECC modules for main data area can be used for (up to) 2048 bytes ECC parity code generation, and 1
bit ECC module for spare area can be used for (up to) 4 bytes ECC Parity code generation.
Both 4bit and 8bit ECC modules can be used for only 512 bytes ECC parity code generation.
4 bit and 8bit ECC modules generate the parity codes for each 512 byte. However, 1 bit ECC modules generate
parity code per byte lane separately.

10.1 ECC MODULE FEATURES

ECC generation is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit of the Control register. When
ECCLock is Low, ECC codes are generated by the H/W ECC modules.
Bit [31:24] Bit [23:16]
th rd
4 I/O[ 7:0] 3 I/O[ 7:0]
Bit [31:24] Bit [23:16]
Invalid value Invalid value
Bit [31:24] Bit [23:16]
Invalid value Invalid value
NAND FLASH CONTROLLER
Bit [15:8] Bit [7:0]
nd st
2 I/O[ 7:0] 1 I/O[ 7:0]
Bit [15:8] Bit [7:0]
nd st
2 I/O[ 7:0] 1 I/O[ 7:0]
Bit [15:8] Bit [7:0]
st
Invalid value
1 I/O[ 7:0]
7-5