Samsung S3C2416 User Manual page 512

HSMMC CONTROLLER
Name
PWRSYNC
ENCLKOUTMSKCON
HWINITFIN
NOTES:
1. Ensure to always set SDCLK Hold Enable (EnSCHold) if the card does not support Read Wait to guarantee for Receive
data not overwritten to the internal FIFO memory.
2. CMD_wo_DAT issue is prohibited during READ transfer when SDCLK Hold Enable is set
20-66
Bit
[3]
SD OP Power Sync Support with SD Card
This field is used to enable input CMD and DAT referencing
SD Bus Power bit in the "PWRCON register", when being set.
0 = No Sync, no switch input enable signal (Command, Data)
1 = Sync, control input enable signal (Command, Data)
[2]
Reserved
[1]
SDCLK output clock masking when Card Insert cleared
This field when High is used not to stop SDCLK when No
Card state.
0 = Disable
1 = Enable
[0]
SD Host Controller Hardware Initialization Finish
0 = Not Finish
1 = Finish
S3C2416X RISC MICROPROCESSOR
Description Initial Value
0
0
0
0