Samsung S3C2416 User Manual page 156

MOBILE DRAM CONTROLLER
3.6.2 DDR2 Memory MRS[15:0] and EMRS(1)[31:16]
PnBANKCON
BA [31:30]
Reserved
Qoff
RDQS
nDQS
OCD program [25:23]
Additive latency [21:19]
Rtt [22] [18]
D.I.C
DLL enable
Reserved [15:13]
Active Power
down exit time
WR [11:9]
DLL Reset
TM
CAS Latency
Burst Type
Burst Length
6-12
Bit
Bank address for EMRS
[29] Should be '0'
0 = Output buffer enable
[28]
1 = Output buffer disable
0 = Disable
[27]
1 = Enable
0 = Enable
[26]
1 = Disable
Refer to DDR2 spec.
Refer to DDR2 spec.
00 = ODT disable
01 = 75Ω
10 = 150Ω
11 = 50Ω
0 = Full strength
[17]
1 = Reduced strength
0 = Enable
[16]
1 = Disable
Should be '0'
0 = Fast exit
[12]
1 = Slow exit
Write recovery for auto pre-charge
0 = No
[8]
1 = Yes
0 = Normal
[7]
1 = Test
CAS Latency for MRS
00 = Reserved
[6:4]
01 = 1-clock
10 = 2-clock
11 = 3-clock
DRAM Burst Type (Read Only)
[3]
Only support sequential burst type.
DRAM Burst Length (Read Only)
[2:0]
This value is determined internally.
S3C2416X RISC MICROPROCESSOR
Description Initial State
10b
0b
0b
0b
0b
000b
000b
00b
0b
0b
000b
0b
000b
0b
0b
000b
0b
011b