Samsung S3C2416 User Manual page 104

SYSTEM CONTROLLER
The CLKSRC selects the source input of the clocks.
CLKSRC Bit
RESERVED [31:19]
SELHSSPI0 [18]
SELHSMMC1 [17]
SELHSMMC0 [16]
RESERVED [15:9]
SELESRC [8:7]
SELEPLL [6]
RESERVED [5]
SELMPLL [4]
SELEXTCLK [3]
RESERVED [2:0]
2-26
-
HS-SPI0 clock
0 = EPLL (divided), 1 = MPLL (divided)
HSMMC1 clock
0 = EPLL (divided), 1 = EXTCLK
HSMMC0 clock
0 = EPLL (divided), 1 = EXTCLK
-
Selection EPLL reference clock
10 = XTAL, 11 = EXTCLK
0x = identical to that of MPLL reference clock
Do not configure SELESRC & SELEPLL register simultaneously.
EsysClk selection
0 = EPLL reference clock, 1 = EPLL output
-
MSYSCLK selection
0 = MPLL reference clock (produced through clock divider)
1 = MPLL output
Configure MPLL reference clock divider
0 = don't use MPLL reference clock divider (means 1/1 divide ratio)
1 = use MPLL reference clock divider (See EXTDIV field of
CLKDIV)
-
S3C2416X RISC MICROPROCESSOR
Description Initial Value
0x0_0000
0
0
0
0
00
0
0
0
0
0x0