Smc Control Register - Samsung S3C2416 User Manual

STATIC MEMORY CONTROLLER
4.9

SMC CONTROL REGISTER

Register
SMCCR
MemClkRatio
SMClockEn
5-20
Address R/W
0x4F000204 R/W
Bit
[31:2] Read undefined. Write as zero.
[1] Defines the ratio of SMCLK to HCLK:
0 = SMCLK = HCLK.
1 = SMCLK = HCLK/2.
[0] SMCLK enable:
0 = Clock only active during memory accesses.
1 = Clock always running.
Clock stopping saves power by stopping SMCLK when it is
not required. If clock stopping is enabled before the memory
access, the SMC stops SMCLK on the following conditions:
asynchronous read access to asynchronous memory
•
asynchronous write access to asynchronous memory
•
asynchronous read access to synchronous memory
•
asynchronous write access to synchronous memory.
•
Description
SMC control register
Description
S3C2416X RISC MICROPROCESSOR
Reset Value
Initial State
0x3
0x0
0x1
0x1