Samsung S3C2416 User Manual page 495

S3C2416X RISC MICROPROCESSOR
Name
STACMDCMPLT
NOTES:
1. Host Driver may check if interrupt is actually cleared by polling or monitoring the INTREQ port. If HCLK is much faster
than SDCLK, it takes long time to be cleared for the bits actually.
2. Card Interrupt status bit keeps previous value until next card interrupt period (level interrupt) and can be cleared when
write to 1 (RW1C).
Bit
The table below shows that Transfer Complete has higher priority
than Data Timeout Error. If both bits are set to 1, the data transfer
can be considered complete.
Relation between Transfer Complete and Data
Transfer
Complete
0
0
1
1 = Data Transfer Complete
0 = No transfer complete
[0]
Command Complete
This bit is set when get the end bit of the command response.
(Except Auto
CMD12) Refer to Command Inhibit (CMD) in the Present State
register.
The table below shows that Command Timeout Error has higher
priority than Command Complete. If both bits are set to 1, it can
be considered that the response was not received correctly.
Command
Complete
0
Don't care
1
1 = Command Complete
0 = No command complete
Description
Data Timeout Meaning of the status
Error
0 Interrupted by another factor
1 Timeout occur during transfer
Don't care Data transfer complete
Command Meaning of the status
Timeout Error
0 Interrupted by another factor
1 Response not received within
64 SDCLK cycles.
0 Response received
HSMMC CONTROLLER
Initial Value
0
20-49