Features - Samsung S3C2416 User Manual

PRODUCT OVERVIEW

2 FEATURES

2.1.1 Architecture
• Integrated system for hand-held devices and
general embedded applications.
• 16/32-Bit RISC architecture and powerful
instruction set with ARM926EJ CPU core.
• Enhanced ARM architecture MMU to support
WinCE, EPOC 32 and Linux.
• Instruction cache, data cache, write buffer and
Physical address TAG RAM to reduce the effect
of main memory bandwidth and latency on
performance.
• ARM926EJ CPU core supports the ARM debug
architecture.
• Internal Advanced Microcontroller Bus
Architecture (AMBA) (AMBA2.0, AHB/APB).
2.1.2 System Manager
• Little/Big Endian support.
• Two independent memory bus - one for the
ROM/SRAM bus (ROM Bank0~Bank5) and one
for the DRAM bus (mSDR/mDDR/DDR2
SDRAM Bank0~Bank1)
• Address space: 64M bytes for Rom bank0 ~
bank5, 128M bytes for SDRAM bank0 ~ bank1.
• Supports programmable 8/16-bit data bus width
for ROM/SRAM bank and programmable 16/32-
bit data bus width for SDRAM bank
• Fixed bank start address from Rom bank 0 to
bank 5 and SDRAM bank 0 to bank1.
• Eight memory banks:
– Six memory banks for ROM, SRAM, and
others (NAND etc.).
– Two memory banks for Synchronous DRAM.
Complete Programmable access cycles for all
•
memory banks.
• Supports external wait signals to expand the bus
cycle.
• Supports self-refresh mode in SDRAM for
power-down.
• Supports various types of ROM for booting
(NOR Flash, EEPROM, OneNAND, IROM and
others).
1-2
S3C2416X RISC MICROPROCESSOR
2.1.3 NAND Flash
• Supports booting from NAND flash memory by
selecting OM as IROM boot mode. (Only 8bit
Nand and 8ECC is supported when it boots)
• 64KB for internal SRAM Buffer(8KB internal
buffer for booting)
• Supports storage memory for NAND flash
memory after booting.
• Supports Advanced NAND flash
2.1.4 Cache Memory
• 64-way set-associative cache with I-Cache
(16KB) and D-Cache (16KB).
• 8words length per line with one valid bit and two
dirty bits per line.
• Pseudo random or round robin replacement
algorithm.
• Write-through or write-back cache operation to
update the main memory.
• The write buffer can hold 16 words of data and
four addresses.
2.1.5 Clock & Power Manager
• On-chip MPLL and EPLL:
EPLL generates the clock to operate USB Host,
IIS, UART, etc.
MPLL generates the clock to operate MCU at
maximum 400MHz @ 1.3 V.
• Clock can be fed selectively to each function
block by software.
• Power mode: Normal, Idle, Stop, Deep Stop and
Sleep mode
Normal mode: Normal operating mode
Idle mode: The clock for only CPU is stopped.
Stop mode: All clocks are stopped.
Deep Stop mode: CPU power is gated and all
clocks are stopped.
Sleep mode: The Core power including all
peripherals is shut down.
• Woken up by EINT[15:0] or RTC alarm & tick
interrupt from Sleep mode and (Deep)STOP
mode.