Samsung S3C2416 User Manual page 106

SYSTEM CONTROLLER
CLKDIV1 configures the clock ratio related on EPLL.
CLKDIV1 Bit
RESERVED [31:26]
SPIDIV_0 [25:24]
DISPDIV [23:16]
I2SDIV_0 [15:12]
UARTDIV [11:8]
HSMMCDIV_1 [7:6]
USBHOSTDIV [5:4]
RESERVED [3:0]
CLKDIV2 configures the clock ratio related on EPLL or MPLL.
CLKDIV2 Bit
RESERVED [31:8]
HSMMCDIV_0 [7:6]
RESERVED
SPIDIV0_MPLL [4:0]
2-28
-
HS-SPI clock divider ratio, ratio = (SPIDIV +1)
Display controller clock divider ratio,
ratio = (DISPDIV + 1)
I2S0 clock divider ratio, ratio = (I2SDIV_0 + 1)
UART clock divider ratio, ratio = (UARTDIV + 1)
HSMMC_1 clock divider ratio, ratio = (HSMMCDIV_1 + 1)
Usb Host clock divider ratio, ratio = (USBHOSTDIV + 1)
-
-
HSMMC_0 clock divider ratio(EPLL), ratio = (HSMMCDIV_1 + 1)
[5] -
HS-SPI0 clock divider ratio(MPLL), ratio = (SPIDIV_1 +1)
S3C2416X RISC MICROPROCESSOR
Description
Description
Initial Value
0
0x0
0x0
0x0
0x0
0x0
0x0
0
Initial Value
0
0x0
0
0