Samsung S3C2416 User Manual page 622

PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR
2 PCM AUDIO INTERFACE
The PCM Audio Interface provides a serial interface to an external Codec. The PCM module receives an input
PCMSOURCE_CLK that is used to generate the serial shift timing. The PCM interface outputs a serial data out, a
serial shift clock, and a sync signal. Data is received from the external Codec over a serial input line. All the serial
data in, serial data out, and sync signal are synchronized to the serial shift clock.
The serial shift clock, PCMSCLK, is generated from a programmable divide of the input PCMSOURCE_CLK. The
sync signal, PCMFSYNC, is generated based upon a programmable number of serial clocks and is one serial
data clock wide.
The PCM data words are 16-bits wide and serially shifted out 1-bit per PCMSCLK. Only one 16-bit word is shifted
out for each PCMFSYNC. The PCMSCLK will continue to toggle even after all 16-bits have been shifted out. The
PCMSOUT data will be a undefined after the 16-bit word has completed. The next PCMFSYNC will signal the
start of the next PCM data word.
The TX FIFO provides the 16-bit data word to be serially shifted out. This data is serially shifted out MSB first, one
bit per PCMSCLK. The PCM serial output data, PCMSOUT, is clocked out using the rising edge of the
PCMSCLK. The MSB bit position relative to the PCMFSYNC is programmable to be either coincident with the
PCMFSYNC or one PCMSCLK later. After all 16-bits have been shifted out, an interrupt can optionally be
generated indicating the end of the transfer.
When the data is being shifted out, the PCMSIN input is used to serially shift data in from the external codec. The
data is received MSB first and is clocked in the falling edge of PCMSCLK. The position of the first bit is
programmable to be coincident with the PCMFSYNC or one PCMSCLK later.
The first 16-bits are serially shifted into the PCM_DATAIN register which is later loaded into the RX FIFO.
Subsequent bits are ignored until the next PCMFSYNC.
Various Interrupts are available to indicate the status of the RX and TX FIFO. Each FIFO has a programmable
flag to indicate when the CPU needs to service the FIFO. For the RX FIFO there is an interrupt which will be
raised when the FIFO exceeds a certain programmable almost_full depth. Similarly there is a programmable
almost_empty interrupt for the TX FIFO.
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