Samsung S3C2416 User Manual page 485

16/32-bit risc
Table of Contents

Advertisement

S3C2416X RISC MICROPROCESSOR
Name
Bit
There are three cases to restart the transfer after stop at the block gap. Which case is appropriate depends on
whether the Host Controller issues a Suspend command or the SD card accepts the Suspend command.
(1) If the Host Driver does not issue a Suspend command, the Continue Request shall be used to restart the
transfer.
(2) If the Host Driver issues a Suspend command and the SD card accepts it, a Resume command shall be used
to restart the transfer.
(3) If the Host Driver issues a Suspend command and the SD card does not accept it, the Continue Request
shall be used to restart the transfer.
Any time Stop At Block Gap Request stops the data transfer, the Host Driver shall wait for Transfer Complete
(in the Normal Interrupt Status register) before attempting to restart the transfer. When restarting the data transfer
by Continue Request, the Host Driver shall clear Stop At Block Gap Request before or simultaneously.
NOTE: After setting Stop at Block Gap Request field, which should not be cleared unless Block Gap Event or Transfer
Complete interrupt occurs. Otherwise, the module hangs.
This bit is used to stop executing a transaction at the next block gap for
both DMA and non-DMA transfers. Until the Transfer Complete is set to
1, indicating a transfer completion the Host Driver shall leave this bit set
to 1.
Clearing both the Stop At Block Gap Request and Continue Request
shall not cause the transaction to restart. Read Wait is used to stop the
read transaction at the block gap. The Host Controller shall honor Stop
At Block Gap Request for write transfers, but for read transfers it
requires that the SD card support Read Wait. Therefore the Host Driver
shall not set this bit during read transfers unless the SD card supports
Read Wait and has set Read Wait Control to 1. In the case of write
transfers in which the Host Driver writes data to the Buffer Data Port
register, the Host Driver shall set this bit after all block data is written. If
this bit is set to 1, the Host Driver shall not write data to Buffer Data Port
register.
This bit affects Read Transfer Active, Write Transfer Active, DAT
Line Active and Command Inhibit (DAT) in the Present State register.
Regarding detailed control of bits D01 and D00. (RW)
'1' = Stop
'0' = Transfer
Description
HSMMC CONTROLLER
Initial Value
20-39

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents