Dma Status Register (Dstat) - Samsung S3C2416 User Manual

DMA CONTROLLER

4.6 DMA STATUS REGISTER (DSTAT)

Register
DSTAT0 0x4B000014
DSTAT1 0x4B000114
DSTAT2 0x4B000214
DSTAT3 0x4B000314
DSTAT4 0x4B000414
DSTAT5 0x4B000514
DSTATn Bit
STAT [21:20]
CURR_TC [19:0]
8-14
Address R/W
R DMA0 Count Register
R DMA1 Count Register
R DMA2 Count Register
R DMA3 Count Register
R DMA4 Count Register
R DMA5 Count Register
Status of this DMA controller.
00 = It indicates that DMA controller is ready for another DMA
request.
01 = It indicates that DMA controller is busy for transfers.
Current value of transfer count.
Note that transfer count is initially set to the value of DCONn[19:0]
register and decreased by one at the end of every atomic transfer.
S3C2416X RISC MICROPROCESSOR
Description
Description
Reset Value
000000h
000000h
000000h
000000h
000000h
000000h
Initial State
00b
00000h