Samsung S3C2416 User Manual page 477

S3C2416X RISC MICROPROCESSOR
Name Bit
INSCARD [16]
[15:14] Reserved
DIFF4W [13]
DIFF1W [12]
BUFRDRDY [11]
0 = Reset or Debouncing
Card Inserted (RO)
This bit indicates whether a card has been inserted. The Host
Controller shall debounce this signal so that the Host Driver will not
need to wait for it to stabilize. Changing from 0 to 1 generates a
Card Insertion interrupt in the Normal Interrupt Status register and
changing from 1 to 0 generates a Card Removal interrupt in the
Normal Interrupt Status register. The Software Reset For All in the
Software Reset register shall not affect this bit. If a card is removed
while its power is on and its clock is oscillating, the Host Controller
shall clear SD Bus Power in the Power Control register and SD
Clock Enable in the Clock Control register.
When this bit is changed from 1 to 0, the Host Controller shall
immediately stop driving CMD and DAT[3:0] (tri-state). In addition,
the Host Driver should clear the Host Controller by the Software
Reset For All in Software Reset register. The card detect is active
regardless of the SD Bus Power.
1 = Card Inserted
0 = Reset or Debouncing or No Card
FIFO Pointer Difference 4-Word (ROC)
When the difference of the address pointer between AHB side and
SD side is more than or equal to 4-word, this status bit is set to
HIGH. When others clears automatically.
Write(Tx) mode : when this bit is HIGH, more than or equal to 4-
word can be written by CPU side.
Read(Rx) mode : when this bit is HIGH, more than or equal to 4-
word can be read by CPU side.
FIFO Pointer Difference 1-Word (ROC)
When the difference of the address pointer between AHB side and
SD side is more than or equal to 1-word, this status bit is set to
HIGH. When others clears automatically.
Write(Tx) mode : when this bit is HIGH, more than or equal to 1-
word can be written by CPU side.
Read(Rx) mode : when this bit is HIGH, more than or equal to 1-
word can be read by CPU side.
Buffer Read Enable (ROC)
This status is used for non-DMA read transfers. The Host Controller
may implement multiple buffers to transfer data efficiently. This read
only flag indicates that valid data exists in the host side buffer status.
If this bit is 1, readable data exists in the buffer. A change of this bit
from 1 to 0 occurs when all the block data is read from the buffer. A
change of this bit from 0 to 1 occurs when block data is ready in the
buffer and generates the Buffer Read Ready interrupt.
1 = Read enable
0 = Read disable
Description
HSMMC CONTROLLER
Initial Value
0
0
0
0
20-31