Bank Control Registers 0-5 - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR
4.6

BANK CONTROL REGISTERS 0-5

Register
0x4F000014
SMBCR0
SMBCR1 0x4F000034
0x4F000054
SMBCR2
0x4F000074
SMBCR3
0x4F000094
SMBCR4
0x4F0000B4
SMBCR5
DELAYnCS
AddrValid
WriteEn
BurstLenWrite
SyncWriteDev
BMWrite
DRnOWE
Reserved
Reserved
AddrValid
ReadEn
Address R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
[31:26] Read undefined. Write as zero.
[25:22] Controls the delay between ADDR signal and nCS signal. The
field is valid only when DRnCS bit is 1.
[21] not available(should be high)
[20] Controls the behavior of the signal RSMAVD during write
operations:
0 = Signal always HIGH
1 = Signal active for asynchronous and synchronous write
accesses (default).
[19:18] Burst transfer length. Sets the number of sequential transfers
that the burst device supports for a write:
00 = 4-transfer burst (default)
01 = Reserved
10 = Reserved
11 = Reserved
[17] 0 = Asynchronous device (default).
1 = Synchronous device.
[16] Burst mode write:
0 = Nonburst writes to memory devices (default at reset)
1 = Burst mode writes to memory devices.
[15]
0 = No delay (default)
1 = Get the delay between nCS signal and nOE/nWE signal.
nOE: The number of cycle is defined by SMBWSTOENRx
which must be larger than 1.
nWE: The number of cycle is defined by SMBWSTWENRx
which must be larger than 1.
This bit is applied only when nWAIT signal is used.
[14] Reserved
[13] not available(should be high)
[12] Controls the behavior of the signal RSMAVD during read
operations:
0 = Signal always HIGH.
1 = Signal active for asynchronous and synchronous read
accesses (default).
Description
Bank0 control register
Bank1 control register
Bank2 control register
Bank3 control register
Bank4 control register
Bank5 control register
Description
STATIC MEMORY CONTROLLER
Reset Value
See note in p5-17
0x303000
0x303010
0x303000
0x303010
0x303010
Initial State
0x0
0x0
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x1
0x1
5-17