Samsung S3C2416 User Manual page 439

S3C2416X RISC MICROPROCESSOR
Register
Clk_CFG(Ch0) 0x52000004
Clk_CFG
ClkSel [10:9]
ENCLK
Prescaler Value [7:0]
Address R/W
R/W
Bit
Clock source selection to generate HS_SPI clock-out
00 = PCLK
01 = USBCLK
10 = Epll clock
11 = Reserved
*
For using USBCLK source, The USB_SIG_MASK at system controller
should be set to on.
* Epll clock is from System Controller and has 4 sources:
MOUT DOUT
EPLL,
[8] Clock on/off
0 = Disable
1 = Enable
HS_SPI clock-out division rate
HS_SPI clock-out = Clock source / ( 2 x (Prescaler value +1))
Description
Clock configuration register
Description
PLL_SRCLK, CLK27M
MPLL,
HS_SPI CONTROLLER
Reset Value
0x0
Initial State
2'b0
1'b0
8'h0
19-7