Pcm Clk Control Register - Samsung S3C2416 User Manual

PCM AUDIO INTERFACE

3.5 PCM CLK CONTROL REGISTER

Register
PCM_CLKCTL
The bit definitions for the PCM_CTL Control Register are shown below:
PCM_CLKCTL
Reserved
CTL_SERCLK_EN
CTL_SERCLK_SEL
SCLK_DIV
SYNC_DIV
NOTE: For correct functioning of PCM pause and continue, please refer following steps.
To Pause PCM operation, first set CTL_SERCLK_EN = 0x0, then set PCM_PCM_ENABLE =0x0.
To continue PCM operation, first set CTL_SERCLK_EN = 0x1, then set PCM_PCM_ENABLE =0x1.
25-8
Address R/W
0x5C000004 R/W
Bit
[31:20]
Reserved
[19]
Enable the serial clock division logic.
Must be HIGH for the PCM to operate (if it is high, PCMSCLK
and PCMFSYNC is operated.) 1)
[18]
Select the source of the PCMSOURCE_CLK
0 = External clock
1 = PCLK
[17:9]
Controls the divider used to create the PCMSCLK based on
the PCMSOURCE_CLK. (1/2~1/1024) PCMSLCK will be
PCMSOURCE_CLK / 2*(SCLK_DIV+1)
[8:0]
Controls the frequency of the PCMFSYNC signal based on
the PCMSCLK. (1/1~1/512)
Freq. of PCMFSYNC = Freq. of PCMSCLK/(SYNC_DIV+1)
Description
Control the PCM Audio Inteface
Description
S3C2416X RISC MICROPROCESSOR
Reset Value
0x00000000
Initial State
0
0
000
000