Nand Flash Access - Samsung S3C2416 User Manual

NAND FLASH CONTROLLER
Figure 7-4. nWE & nRE Timing (TWRPH0=0, TWRPH1=0) Block Diagram

7 NAND FLASH ACCESS

S3C2416 does not support NAND flash access mechanism directly. It only supports signal control mechanism for
NAND flash access. Therefore software is responsible for accessing NAND flash memory correctly.
1. Writing to the command register (NFCMMD) = the NAND Flash Memory command cycle
2. Writing to the address register (NFADDR) = the NAND Flash Memory address cycle
3. Writing to the data register (NFDATA) = write data to the NAND Flash Memory (write cycle)
4. Reading from the data register (NFDATA) = read data from the NAND Flash Memory (read cycle)
5. Reading main ECC registers and Spare ECC registers (NFMECCD0/1, NFSECCD) = read data from the
NAND Flash Memory
In NAND flash access, you must check the RnB status input pin by polling the signal or using interrupt.
7-4
HCLK
nWE / nRE
DATA
TWRPH0 TWRPH1
DATA
NOTE
S3C2416 RISC MICROPROCESSOR