Samsung S3C2416 User Manual page 32

PRODUCT OVERVIEW
2 FEATURES (Continued)
2.1.13 A/D Converter & Touch Screen Interface
• 10-ch multiplexed ADC
• Max. 500KSPS and 12-bit Resolution
• Internal FET for direct Touch screen interface
2.1.14 Watchdog Timer
• 16-bit Watchdog Timer
• Interrupt request or system reset at time-out
2.1.15 IIC-Bus Interface
• 1-ch Multi-Master IIC-Bus
• Serial, 8-bit oriented and bi-directional data
transfers can be made at up to 100 Kbit/s in
Standard mode or up to 400 Kbit/s in Fast mode.
2.1.16 2D
• Line/Point Drawing
• BitBLT, Color Expansion.
• Maximum 2040*2040 image size
• Window clipping
• 90°/180°/270°/X-flip/Y-flip Rotation
• Totally 256 3-operand Raster Operation (ROP)
• Alpha Blending
• 16/24/32-bpp color format support
• YUV input support (4:2:2, 2-planar)
2.1.17 IIS Multi Audio Interface
• 1 ports audio interface with DMA-based
operation.
• Up to 5.1ch, three 32bit 16depth Tx FIFOs, One
32bit 16depth Rx FIFO
• Serial, 8-/16-/24- bit per channel data transfers
• Supports IIS format and MSB-justified data
format
2.1.18 AC97 Audio Interface
• 1port AC97 for audio interface with DMA-based
operation
• 16-bit Stereo Audio
2.1.19 PCM Audio Interface
• Mono, 16bit PCM, 1 ports audio interface.
• Master mode only, this block always sources the
main shift clock
• Input (16bit 32depth) and output(16bit 32depth)
1-4
S3C2416X RISC MICROPROCESSOR
FIFOs to buffer data
2.1.20 USB Host
• 2-port USB Host
Complies with OHCI Rev. 1.0
•
• Compatible with USB Specification version 1.1
2.1.21 USB Device
• 1-port USB Device
• 9 Endpoints for USB Device
• Compatible with USB Specification version 2.0
2.1.22 SD/MMC Host Interface
• SD Standard Host Spec(ver2.0) compatible
• Dedicated DMA access support
• Compatible with SD Memory Card Protocol
version 2.1
• Compatible with SDIO Card Protocol version 1.0
• Compatible with HS-MMC Protocol version 4.2
• 512 Bytes FIFO for Tx/Rx
• CE-ATA mode support
2.1.23 SPI Interface
• Compatible with 1-ch Serial Peripheral Interface
Protocol version 2.11 (1ch. High speed SPI
interface)
• 2x8 bits Shift register for Tx/Rx
• DMA-based or interrupt-based operation
2.1.24 Operating Voltage Range
• Core: 1.3V for 400MHz
TBD for 266MHz
ROM/SRAM: 1.8V/ 2.5V/ 3.0V/ 3.3V
SDRAM: 1.8V/ 2.5V
• I/O: 1.8V/2.5V/3.3V(refer to electrical data)
2.1.25 Operating Frequency
• FCLK Up to 400(266)MHz
• HCLK Up to 133MHz
• PCLK Up to 67MHz
2.1.26 Package
• 330 FBGA 14x14