Dclk Control Registers (Dclkcon) - Samsung S3C2416 User Manual

I/O PORTS

3.13 DCLK CONTROL REGISTERS (DCLKCON)

Register
DCLKCON
DCLKCON
Reserved
DCLK1CMP
DCLK1DIV
DCLK1SelCK
DCLK1EN
DCLK0CMP
DCLK0DIV
DCLK0SelCK
DCLK0EN
10-30
Address R/W
0x56000084 R/W
Bit
[31:28] Reserved
[27:24] DCLK1 compare value clock toggle value. ( < DCLK1DIV)
If the DCLK1CMP is n, Low level duration is( n + 1),
High level duration is((DCLK1DIV + 1) –( n +1))
[23:20] DCLK1 divide value
DCLK1 frequency = source clock /( DCLK1DIV + 1)
[17] Select DCLK1 source clock
0 = PCLK
1 = EPLL
[16] DCLK1 enable
0 = DCLK1 disable
1 = DCLK1 enable
[11:8] DCLK0 compare value clock toggle value.( < DCLK0DIV)
If the DCLK0CMP is n, Low level duration is( n + 1),
High level duration is((DCLK0DIV + 1) –( n +1))
[7:4] DCLK0 divide value.
DCLK0 frequency = source clock /( DCLK0DIV + 1)
[1] Select DCLK0 source clock
0 = PCLK
1 = EPLL
[0] DCLK0 enable
0 = DCLK0 disable
1 = DCLK0 enable
DCLKnCMP + 1
Description
DCLK0/1 control register
Description
DCLKnDIV + 1
S3C2416 RISC MICROPROCESSOR
Reset Value
0x0