Miscellaneous Control Register (Misccr) - Samsung S3C2416 User Manual

S3C2416 RISC MICROPROCESSOR

3.12 MISCELLANEOUS CONTROL REGISTER (MISCCR)

In Sleep mode, the data bus(SD[15:0] or RD[15:0] can be set as Hi-Z and Output '0' state. But, because of the
characteristics of IO pad, the data bus pull-up/down resisters have to be turned on or off to reduce the power
consumption. SD[15:0] or RD[15:0] pin pull-up/down resisters can be controlled by MISCCR register.
Pads related USB are controlled by this register for USB host, or for USB device.
Register
MISCCR
MISCCR
HSSPI_EN2
Reserved
Reserved
Reserved
Reserved
FLT_I2C
Reserved
SEL_SUSPND
Reserved
CLKSEL1 *
Reserved
CLKSEL0 *
Reserved
NOTES:
1. User must set first MISCCR[31] = 1'b1 when use the high speed SPI.
2. We recommend not using this output pad to other device's pll clock source.
Address R/W
0x56000080 R/W
Bit
[31] Must be set '1'
[30] Reserved
[29] Reserved
[28] Should be '1'
[27:25] Reserved
[24] Clocked Noise Filter Enable for IIC
[23:13] Reserved
[12] USB Port Suspend mode
0 = Normal mode
1 = Suspend mode
[11] Reserved
[10:8] Select source clock with CLKOUT1 pad
000 = RESERVED
001 = Gated EPLL output
010 = RTC clock output
011 = HCLK
100 = PCLK
101 = DCLK1(Divided PCLK)
11x = Reserved
[7] Reserved
[6:4] Select source clock with CLKOUT0 pad
000 = MPLL INPUT Clock(XTAL)
001 = EPLL output
010 = FCLK(ARMCLK)
011 = HCLK
100 = PCLK
101 = DCLK0 (Divided PCLK)
110 = OSC To PLL INPUT Clock
111 = Reserved
[3:0] Reserved
Description
Miscellaneous control register
Description
I/O PORTS
Reset Value
0xd0000020
Reset Value
1
1
0
1
000
0
0
0
0
000
0
010
0
10-29