Iis Mode Register (Iismod) - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

8.2 IIS MODE REGISTER (IISMOD)

Register
IISMOD
IISMOD
Reserved [31:15]
CDD2 [21:20]
CDD1 [19:18]
DCE [17:16]
BLC [14:13]
CDCLKCON
IMS [11:10]
23-18
Address
0x55000004 IIS interface mode register
Bit R/W
R/W Reserved. Program to zero.
R/W
Channel-2 Data Discard. Discard means zero padding. It only supports
8/16 bit mode.
00 = No Discard
01 = I2STXD[15:0] Discard
10 = I2STXD[31:16] Discard
11 = Reserved
R/W
Channel-1 Data Discard. Discard means zero padding. It only supports
8/16 bit mode.
00 = No Discard
01 = I2STXD[15:0] Discard
10 = I2STXD[31:16] Discard
11 = Reserved
R/W
Data Channel Enable.
[17] = SD2 channel enable
[16] = SD1 channel enable
[15] R/W Reserved, Program to Zero
R/W
Bit Length Control Bit Which decides transmission of 8/16 bits per
audio channel
00 = 16 Bits per channel
01 = 8 Bits Per Channel
10 = 24 Bits Per Channel
11 = Reserved
[12] R/W
Determine direction of codec clock(I2SCDCLK)
0 = Supply codec clock to external codec chip.
1 = Get codec clock from external codec chip. (to CLKAUDIO)
R/W IIS master or slave mode select. (and select source of codec clock)
00 = Master mode
01 = Master mode
10 = Slave mode (PCLK is source clock for I2SCDCLK)
11 = Slave mode
Description
(from PCLK, EPLL, EPLLRefCLK)
(Refer to Figure 23-2)
(PCLK is source clock for I2SSCLK, I2SLRCLK, I2SCDCLK)
(CLKAUDIO is source clock for I2SSCLK, I2SLRCLK.
CLKAUDIO-EPLL, EPLLRefCLK is source clock for I2SCDCLK)
(CLKAUDIO-EPLL, EPLLRefCLK is source clock for I2SCDCLK)
(Refer to Figure 23-2)
S3C2416X RISC MICROPROCESSOR
Description
Reset Value
0x0000_0000