Table of Contents
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Chapter 20
5.13 Block Gap Control Register ...........................................................................................................20-38
5.14 Wakeup Control Register...............................................................................................................20-40
5.15 Clock Control Register...................................................................................................................20-41
5.16 Timeout Control Register...............................................................................................................20-43
5.17 Software Reset Register................................................................................................................20-44
5.18 Normal Interrupt Status Register ...................................................................................................20-46
5.19 Error Interrupt Status Register.......................................................................................................20-50
5.20 Normal Interrupt Status Enable Register.......................................................................................20-53
5.21 Error Interrupt Status Enable Register ..........................................................................................20-55
5.22 Normal Interrupt Signal Enable Register .......................................................................................20-56
5.23 Error Interrupt Signal Enable Register...........................................................................................20-58
5.24 Autocmd12 Error Status Register ..................................................................................................20-59
5.25 Capabilities Register......................................................................................................................20-61
5.26 Maximum Current Capabilities Register ........................................................................................20-63
5.27 Control Register 2 ..........................................................................................................................20-64
5.28 Control Register 3 ..........................................................................................................................20-67
5.29 Debug Register ..............................................................................................................................20-68
5.30 Control Register 4 ..........................................................................................................................20-68
5.31 Force Event Register for Auto CMD12 Error Status......................................................................20-69
5.32 Force Event Register for Error Interrupt Status .............................................................................20-70
5.33 ADMA Error Status Register..........................................................................................................20-71
5.34 ADMA System Address Register...................................................................................................20-73
5.35 HOST Controller Version Register ................................................................................................20-74
1 Overview....................................................................................................................................................21-1
1.1 Features...........................................................................................................................................21-2
2 Functional Description...............................................................................................................................21-3
2.1 Brief of the sub-block .......................................................................................................................21-3
2.2 Data Flow.........................................................................................................................................21-3
2.3 Interface ...........................................................................................................................................21-4
2.4 Overview of the Color Data..............................................................................................................21-5
2.5 VD signal Connection ......................................................................................................................21-18
2.6 Palette usage ...................................................................................................................................21-20
3 Window Blending.......................................................................................................................................21-22
3.1 Overview ..........................................................................................................................................21-22
3.2 Blending Diagram/Details ................................................................................................................21-23
4 Vtime Controller Operation........................................................................................................................21-26
4.1 RGB Interface ..................................................................................................................................21-26
4.2 I80-System Interface........................................................................................................................21-26
5 Virtual Display ...........................................................................................................................................21-27
6 RGB Interface I/O......................................................................................................................................21-28
7 LCD CPU Interface I/O (I80-system I/F) ...................................................................................................21-29
8 Programmer's Model .................................................................................................................................21-31
8.1 Overview ..........................................................................................................................................21-31
xiv
Table of Contents
SD/MMC Host Controller
(Continued)
(Continued)
S3C2416X RISC MICROPROCESSOR
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