HSMMC CONTROLLER
3 BLOCK DIAGRAM
INTREQ
System Bus
(AHB)
20-2
HCLK
Domain
SFR
R
Status
CMD
ARG
Control
G
AHB slave I/F
DMA
controller
AHB master
Figure 20-1. HSMMC Block Diagram
BaseCLK
Clock Control
Line
Control
FIFO
Control
DPSRAM
S3C2416X RISC MICROPROCESSOR
SDCLK
Domain
Status
RSP
CMDRSP
packet
Control
Control
Status
DATA
packet
Pad
I/F