Block Diagram - Samsung S3C2416 User Manual

UART

2 BLOCK DIAGRAM

Peripheral BUS
14-2
Transmitter
Transmit Buffer
Register(64 Byte)
Transmit Shifter
Control Buad-rate
Unit Generator
Receiver
Receive Shifter
Receive Buffer
Register(64 Byte)
In FIFO mode, all 64 Byte of Buffer register are used as FIFO register.
In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register.
Figure 14-1. UART Block Diagram (with FIFO)
S3C2416X RISC MICROPROCESSOR
Transmit FIFO Register
(FIFO mode)
Transmit Holding Register
(Non-FIFO mode)
Clock Source
(PCLK, EXTUARTCLK, EPLL clock/n)
Receive Holding Register
(Non-FIFO mode only)
Receive FIFO Register
(FIFO mode)
TXDn
RXDn