Multi-Master Iic-Bus Address (Iicadd) Register; Multi-Master Iic-Bus Transmit/Receive Data Shift (Iicds) Register - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

2.3 MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER

Register
IICADD0 0x54000008
IICADD0
Bit
IICADD1
Slave address [7:0]

2.4 MULTI-MASTER IIC-BUS TRANSMIT/RECEIVE DATA SHIFT (IICDS) REGISTER

Register
IICDS0 0x5400000C
IICDS0
Bit
IICDS1
Data shift [7:0]
Address R/W
R/W IIC0-Bus address register
7-bit slave address, latched from the IIC-bus.
When serial output enable = 0 in the IICSTAT, IICADD is write-
enabled. The IICADD value can be read any time, regardless of the
current serial output enable bit (IICSTAT) setting.
Slave address : [7:1]
Not mapped : [0]
Address R/W
R/W IIC0-Bus transmit/receive data shift register
8-bit data shift register for IIC-bus Tx/Rx operation.
When serial output enable = 1 in the IICSTAT, IICDS is write-
enabled. The IICDS value can be read any time, regardless of the
current serial output enable bit (IICSTAT) setting.
Description
Description
Description
Description
IIC-BUS INTERFACE
Reset Value
0xXX
Initial State
XXXXXXXX
Reset Value
0xXX
Initial State
XXXXXXXX
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