Synchronous Write/ Synchronous Burst Write - Samsung S3C2416 User Manual

STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR
3.5

SYNCHRONOUS WRITE/ SYNCHRONOUS BURST WRITE

Figure 5-11 shows an example synchronous write operation. In this example the signal SMADDRVALID provides
a one-cycle pulse. This behavior is enabled by setting the SyncWriteDev bit in the SMBCRx register. You must
also set the AddrValidWriteEn bit for synchronous write.
The signal PnWE is only active for one cycle. This is active at the start of the transfer unless it is delayed using
the control bits WSTWEN to delay it.
Synchronous burst writes are supported by the SMC. There is no write buffer so you must delay the AHB transfer
to enable the data to be output onto the SMDATA bus. You can control the write in the same way as reads using
the bits AddrValidWriteEn, BurstLenWrite, SyncEnWrite, and BMWrite contained in the Bank Control Register,
SMCRx.
Synchronous Write
SMCLK
ADDR A
DATA(OUT) D(A)
SMAVD
nCS
WSTWR=3
nWE
WSTWEN=2
Figure 5-11. Synchronous Two Wait State Write
5-10