Capabilities Register - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

5.25 CAPABILITIES REGISTER

This register provides the Host Driver with information specific to the Host Controller implementation. The Host
Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer
to Software Reset for All in the Software Reset register for loading from flash memory and completion timing
control.
Register Address
CAPAREG0 0X4AC00040
CAPAREG1 0X4A800040
Name
CAPAV18
CAPAV30
CAPAV33
CAPASUSRES
CAPADMA
CAPAHSPD
R/W
HWInit Capabilities Register (Channel 0)
HWInit Capabilities Register (Channel 1)
Bit
[31:27] Reserved
[26] Voltage Support 1.8V (HWInit)
1 = 1.8V Supported
0 = 1.8V Not Supported
[25] Voltage Support 3.0V (HWInit)
1 = 3.0V Supported
0 = 3.0V Not Supported
[24] Voltage Support 3.3V (HWInit)
1 = 3.3V Supported
0 = 3.3V Not Supported
[23] Suspend/Resume Support (HWInit)
This bit indicates whether the Host Controller supports
Suspend / Resume functionality. If this bit is 0, the Suspend
and Resume mechanism are not supported and the Host
Driver shall not issue either Suspend or Resume commands.
1 = Supported
0 = Not Supported
[22] DMA Support (HWInit)
This bit indicates whether the Host Controller is capable of
using DMA to transfer data between system memory and the
Host Controller directly.
1 = DMA Supported
0 = DMA Not Supported
[21] High Speed Support (HWInit)
This bit indicates whether the Host Controller and the Host
System support High Speed mode and they can supply SD
Clock frequency from 25MHz to 50MHz.
1 = High Speed Supported
0 = High Speed Not Supported
[20:18] Reserved
Description
Description
HSMMC CONTROLLER
Reset Value
0x05E80080
0x05E80080
Initial Value
1
0
1
1
1
1
20-61