Samsung S3C2416 User Manual page 157

S3C2416X RISC MICROPROCESSOR
3.6.3 DDR2 Memory EMRS(2)[31:16]
PnBANKCON
BA [31:30]
Reserved [29:24]
SRF
Reserved [22:20]
DCC
PASR [18:16]
3.6.4 DDR2 Memory EMRS(3)[31:16]
PnBANKCON
BA [31:30]
Reserved [29:16]
Bit
Bank address for EMRS
Should be '0'
High Temperature Self-Refresh Rate Enable
[23]
0 = Disable
1 = Enable
Should be '0'
0 = Disable
[19]
1 = Enable
PASR(Partial Array Self Refresh) for EMRS(2)
Bit
Bank address for EMRS
Should be '0'
Description
Description
MOBILE DRAM CONTROLLER
Initial State
10b
000000b
0b
000b
0b
000b
Initial State
10b
0x0
6-13