S3C2416X RISC MICROPROCESSOR
5.21 ERROR INTERRUPT STATUS ENABLE REGISTER
Setting to 1 enables Error Interrupt Status.
Register
ERRINTSTSEN0
ERRINTSTSEN1
Name
ADMAERR
ENSTAACMDERR
ENSTACURERR
ENSTADENDERR
ENSTADATCRCERR
ENSTADATTOUTERR
ENSTACMDIDXERR
ENSTACMDEBITERR
ENSTACMDCRCERR
ENSTACMDTOUTERR
Address
R/W
0X4AC00036
R/W
0X4A800036
R/W
Bit
[15:10] Reserved
[9]
ADMA Error Status Enable
1 = Enabled
0 = Masked
[8]
Auto CMD12 Error Status Enable
1 = Enabled
0 = Masked
[7]
Current Limit Error Status Enable
This function is not implemented in this version.
1 = Enabled
0 = Masked
[6]
Data End Bit Error Status Enable
1 = Enabled
0 = Masked
[5]
Data CRC Error Status Enable
1 = Enabled
0 = Masked
[4]
Data Timeout Error Status Enable
1 = Enabled
0 = Masked
[3]
Command Index Error Status Enable
1 = Enabled
0 = Masked
[2]
Command End Bit Error Status Enable
1 = Enabled
0 = Masked
[1]
Command CRC Error Status Enable
1 = Enabled
0 = Masked
[0]
Command Timeout Error Status Enable
1 = Enabled
0 = Masked
Description
Error Interrupt Status Enable Register
(Channel 0)
Error Interrupt Status Enable Register
(Channel 1)
Description
HSMMC CONTROLLER
Reset Value
0x0
0x0
Initial Value
0
0
0
0
0
0
0
0
0
0
0
20-55