Samsung S3C2416 User Manual page 93

S3C2416X RISC MICROPROCESSOR
6. System controller request memory controller to enter self refresh mode. It is for preserving contents in
SDRAM.
7. System controller wait for self refresh acknowledge from memory controller.
8. After receiving the self-refresh acknowledge, system controller disables system clocks, and switches
SYSCLK's source to MPLL reference clock.
9. Disables PLLs and Crystal(XTI) oscillation. If OSC_EN_STOP bit in PWRCFG register is 'high' then system
controller doesn't disable crystal oscillation.
10. When PWRMODE[18] register is configured as '1' (Deep-STOP Enabled), ARM_PWRENn signal change to
enable ARM power gating. ARM Core is reset state during STOP mode.
STOP mode Exiting sequence is as follows
1. Enable X-tal Oscillator if it is used, and wait the OSC settle down (around 1ms).
2. After the Oscillator settle-down, the System Clock is fed using the PLL input clock and also enable the PLLs
and waits the PLL locking time
3. Switching the clock source, now the PLL is the clock source.
4. When waking up from Deep-STOP mode, ARM_PWRENn is restored to release ARM power gating. After
producing SYSCLK ARM_RESETn will be released to let ARM work normally.
DRAM has to be in self-refresh mode during STOP and SLEEP mode to retain valid memory data. LCD
must be stopped before STOP and SLEEP mode, because DRAM can't be accessed when it is in self-
refresh mode.
NOTE
SYSTEM CONTROLLER
2-15