Error Interrupt Signal Enable Register - Samsung S3C2416 User Manual

HSMMC CONTROLLER

5.23 ERROR INTERRUPT SIGNAL ENABLE REGISTER

This register is used to select which interrupt status is notified to the Host System as the interrupt. These status
bits all share the same 1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation.
Register
ERRINTSIGEN0 0X4AC0003A
ERRINTSIGEN1 0X4A80003A
Name
ENSIGADMAERR
ENSIGACMDERR
ENSIGCURERR
ENSIGDENDERR
ENSIGDATCRCERR
ENSIGDATTOUTERR
ENSIGCMDIDXERR
ENSIGCMDEBITERR
ENSIGCMDCRCERR
ENSIGCMDTOUTERR
Detailed documents are to be copied from SD Host Standard Spec.
20-58
Address R/W
R/W
R/W
Bit
[15:10] Reserved
[9]
ADMA Error Signal Enable
1 = Enabled
0 = Masked
[8]
Auto CMD12 Error Signal Enable
1 = Enabled
0 = Masked
[7]
Current Limit Error Signal Enable
This function is not implemented in this version.
1 = Enabled
0 = Masked
[6]
Data End Bit Error Signal Enable
1 = Enabled
0 = Masked
[5]
Data CRC Error Signal Enable
1 = Enabled
0 = Masked
[4]
Data Timeout Error Signal Enable
1 = Enabled
0 = Masked
[3]
Command Index Error Signal Enable
1 = Enabled
0 = Masked
[2]
Command End Bit Error Signal Enable
1 = Enabled
0 = Masked
[1]
Command CRC Error Signal Enable
1 = Enabled
0 = Masked
[0]
Command Timeout Error Signal Enable
1 = Enabled
0 = Masked
Description
Error Interrupt Signal Enable Register (Channel 0)
Error Interrupt Signal Enable Register (Channel 1)
Description
S3C2416X RISC MICROPROCESSOR
Reset Value
Initial Value
0x0
0x0
0
0
0
0
0
0
0
0
0
0
0