Control Register 3; Debug Register; Control Register 4 - Samsung S3C2416 User Manual

HSMMC CONTROLLER

5.29 DEBUG REGISTER

Register
DEBUG_0 0X4AC00088
DEBUG_1 0X4A800088
Name Bit
DBGREG [31:0]

5.30 CONTROL REGISTER 4

Register
CONTROL4_0 0x4AC0008C
CONTROL4_1 0x4A80008C
Name Bit
Reserved [31:1]
StaBusy [0]
20-68
Address R/W
R/W
R/W
Debug Register
Read Only Register for Debug Purpose (RO)
Address R/W
R/W
R/W
−
Status Busy
This bit is "High" when the clock domain crossing (HCLK to SDCLK)
operation is processing. This bit is status bit and Read Only (RO)
Description
DEBUG register (Channel 0)
DEBUG register (Channel 1)
Description
Description
Control register 4 (Channel 0)
Control register 4 (Channel 1)
Description
S3C2416X RISC MICROPROCESSOR
Reset Value
Initial Value
Reset Value
Initial Value
Not fixed
Not fixed
Not fixed
0x0
0x0
0
0