Power Saving Modes - Samsung S3C2416 User Manual

SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR
6.2

POWER SAVING MODES

S3C2416 can support various power saving modes. These are Normal mode, idle mode, Stop mode, Deep-stop
mode and Sleep mode.
6.2.1 Normal Mode (General Clock Gating Mode)
In General Clock Gating mode, the On/Off clock gating of the individual clock source of each IP block is performed
by controlling of each corresponding clock source enable bit. The Clock Gating is applied instantly whenever the
corresponding bit (or bits) is changed. (these bits are set or cleared by the main CPU.)
6.2.2 IDLE Mode
In IDLE mode, the clock to CPU core is stopped. To enter the idle mode, User must use ARM926EJ CP15
command (MCR p15, 0, Rd, c7, c0, 4). If user order this command, ARM core prepare to enter into power down
mode. These are draining write buffer, letting memory system is in a quiescent state and confirming all external
interface(AHB interface) is in idle state. After completing above operation, ARM asserted STANBYWFI signal. So,
System Controller of S3C2416 check STANDBYWFI signal is asserted and disabe ARM clock. By doing that,
System can go into idle mode safely. To exit the idle mode, All interrupt sources, RTC ALARM, RTC Tick Counter,
Battery Fault signal should be activated.
6.2.3 STOP mode (Normal and Deep-stop)
In STOP mode, all clocks are stopped for minimum power consumption. Therefore, the PLL and oscillator circuit
are also stopped(oscillator circuit is stopped optionally, see PWRCFG register). The STOP Mode is activated after
the execution of the STORE instruction that enables the STOP Mode bit. The STOP Mode bit should be cleared
after the wake-up from the STOP state for the entering of next STOP Mode. The H/W logic only detects the low-
to-high triggering of the STOP Mode bit.
In Deep-STOP mode ARM core's power is off by using internal power gating. By this way, the static current will be
reduced remarkably compared with STOP mode. To enter the Deep-STOP mode, PWRMODE[18] register should
be configured before entering STOP mode. After waking up from Deep-STOP mode, System controller resets
ARM core only.
To exit from STOP mode, External interrupt, RTC alarm, RTC Tick, or nRESET has to be activated. During the
wake-up sequences, the crystal oscillator and PLL may begin to operate. The crystal-oscillator settle-down-time
and the PLL locking-time is required to provide stabilized ARMCLK. Those time-waits are automatically inserted
by the hardware of S3C2416. During these time-waits, the clock is not supplied to the internal logic circuitry.
STOP mode Entering sequence is as follows
1. Set the STOP Mode bit (by the main CPU)
2. System controller requests bus controller to finish bus transactions of ARM Core.
3. System controller disable ARM clock after getting ARM Down acknowledge.
4. System controller requests bus controller to finish current transactions.
5. Bus controller send acknowledge to system controller after completed bus transactions.
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