Samsung S3C2416 User Manual page 55

S3C2416X RISC MICROPROCESSOR
Signal
JTAG TEST LOGIC
nTRST
TMS
TCK
TDI
TDO
RTCK
Power
VDDalive
VDDiarm
VDDi
VDDA_MPLL
VDDA_EPLL
VDD_SDRAM
VDD_SRAM
VDD_OP1
VDD_OP2
VDD_OP3
VDD_LCD
VDD_SD
VDD_RTC
VDDA_ADC
VSSi/VSSiarm
VSSA_MPLL
VSSA_EPLL
VSS_SDRAM
VSS_SRAM
VSS_OP1
VSS_OP2
VSS_OP3
VSS_LCD
VSS_SD
In/Out
I nTRST (TAP Controller Reset) resets the TAP controller at start.
If debugger is used, A 10K pull-up resistor has to be connected.
If debugger (black ICE) is not used, nTRST pin must be issued by a low
active pulse (Typically connected to nRESET).
I TMS (TAP Controller Mode Select) controls the sequence of the TAP
controller's states.
I TCK (TAP Controller Clock) provides the clock input for the JTAG logic.
I TDI (TAP Controller Data Input) is the serial input for test instructions and
data.
O TDO (TAP Controller Data Output) is the serial output for test instructions
and data.
O Returned Clock
P S3C2416X reset block and port status register VDD.
It should be always supplied whether in normal mode or in Sleep mode.
P S3C2416X core logic VDD for ARM core.
P S3C2416X core logic VDD for Internal block.
P S3C2416X MPLL analog and digital VDD.
P S3C2416X EPLL analog and digital VDD
P S3C2416X SDRAM I/O Power (1.8V/ 2.5V)
P S3C2416X ROM/SRAM I/O Power
P S3C2416X System I/O Power 1 (1.8 ~ 3.3V)
P S3C2416X System I/O Power 2 ( 1.8 ~ 3.3V)
P S3C2416X System I/O Power 3 ( 1.8 ~ 3.3V)
P S3C2416X LCD I/O Power (1.8 ~ 3.3V)
P S3C2416X SD/MMC I/O Power (1.8 ~ 3.3V)
P RTC VDD (3.0V, Input range: 1.8 ~ 3.6V)
This pin must be connected to power properly if RTC isn't used.
P S3C2416X ADC VDD(3.3V)
G S3C2416X core logic VSS
G S3C2416X MPLL analog and digital VSS.
G S3C2416X EPLL analog and digital VSS
G S3C2416X SDRAM I/O Ground
G S3C2416X ROM/SRAM I/O Ground
G S3C2416X System I/O Ground
G S3C2416X System I/O Ground
G S3C2416X System I/O Ground
G S3C2416X LCD I/O Ground
G S3C2416X SD/MMC I/O Ground
Description
PRODUCT OVERVIEW
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