IIC-BUS INTERFACE
17-10
START
Slave Rx mode has been
configured.
IIC detects start signal. and, IICDS
receives data.
IIC compares IICADD and IICDS (the
received slave address).
Matched?
Y
The IIC address match
interrupt is generated.
Read data from IICDS.
Clear pending bit to
resume.
Stop?
N
SDA is shifted to IICDS.
Interrupt is pending.
Figure 17-9. Operations for Slave/Receiver Mode
S3C2416X RISC MICROPROCESSOR
N
Y
END