Timeout Control Register - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

5.16 TIMEOUT CONTROL REGISTER

At the initialization of the Host Controller, the Host Driver shall set the Data Timeout Counter Value according to
the Capabilities register.
Register
TIMEOUTCON 0 0X4AC0002E
TIMEOUTCON 1 0X4A80002E
Name Bit
[7:4]
TIMEOUTCON [3:0]
Address R/W
R/W
R/W
Reserved
Data Timeout Counter Value
This value determines the interval by which DAT line timeouts are
detected. Refer to the Data Timeout Error in the Error Interrupt
Status register for information on factors that dictate timeout
generation. Timeout clock frequency will be generated by dividing the
base clock SDCLK value by this value. When setting this register,
prevent inadvertent timeout events by clearing the Data Timeout
Error Status Enable (in the Error Interrupt Status Enable register)
1111b Reserved
1110b SDCLK x 2
1101b SDCLK x 2
.............. ...
0001b SDCLK x 2
0000b SDCLK x 2
Description
Timeout Control Register (Channel 0)
Timeout Control Register (Channel 1)
Description
27
26
14
13
HSMMC CONTROLLER
Reset Value
0x0
0x0
Initial Value
0
0
20-43