Master/Slave Mode - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE

5.1 MASTER/SLAVE MODE

Master or slave mode can be chosen by setting IMS bit of IISMOD register. In master mode, I2SSCLK and
I2SLRCLK are generated internally and supplied to external device. Therefore a root clock is needed for
generating I2SSCLK and I2SLRCLK by dividing. The IIS pre-scaler (clock divider) is employed for generating a
root clock with divided frequency from internal system clock(PCLK, divided EPLL clock , EPLLrefCLK) and
external I2S clock(from I2SCDCLK pad). The I2SSCLK and I2SLRCLK are supplied from the pin (GPIOs) in slave
mode.
Master/Slave mode is different with TX/RX. Master/Slave mode presents the direction of I2SLRCLK and
I2SSCLK. It doesn't matter the direction of I2SCDCLK (This is only auxiliary.) At slave mode, I2SCDCLK can be
also going out for external IIS codec chip operation. If IIS bus interface transmits clock signals to IIS codec, IIS
bus is master mode. But if IIS bus interface receives clock signal from IIS codec, IIS bus is slave mode. TX/RX
mode indicates the direction of data flow. If IIS bus interface transmits data to IIS codec, this is TX mode.
Conversely, IIS bus interface receives data from IIS codec that is RX mode. Let's distinguish Master/Slave mode
from TX/RX mode.
Figure 23-2 shows the route of the root clock with internal master(PCLK, divided EPLL clock , EPLLRefClock) or
external master(External I2S clock) mode setting in IIS clock control block and system controller. Note that RCLK
indicates root clock and this clock can be supplied to external IIS codec chip at internal master mode and slave
mode.(when CDCLKCON bit of IISMOD register is 1). At slave mode RCLK doesn't affect to I2SSCLK and
I2SLRCLK, but for correct I2S functioning setting RFS, BFS are needed.
Figure 23-2. IIS Clock Control Block Diagram
23-3