Dma Interface Control Register (Dicr) - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

8.21 DMA INTERFACE CONTROL REGISTER (DICR)

The AHB Master Operation is controlled by the programming DMA Control Register and DMA IF Control Register.
Register Address
DICR 0x4980_0084
DICR Bit
Reserved [31:4]
RELOAD_ [4]
MBAR
Reserved [3:2]
MAX_BURST [1:0]
R/W
R/W DMA Interface Counter Register
R/W
Reserved
−
R/W Select Reload Condiion
0 = Every end of Full DMA operation
1 = Every Packet transfer.
Reserved
R/W Max Burst Length
00 = Single transfer
01 = 4-beat incrementing burst transfer(INCR4)
10 = 8-beat incrementing burst transfer(INCR8)
11 = 16-beat incrementing burst transfer(INCR16)
Description
Description
USB2.0 DEVICE
Reset Value
0x0
Initial State
0
0
0
00
16-29