Processor Exceptions; Access Error Exception; Fault Status Encodings - Motorola ColdFire MCF5281 User Manual

• There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is
defined for access and address errors only and written as zeros for all other types of
exceptions. See Table 2-7.
• The 8-bit vector number, vector[7:0], defines the exception type and is calculated by
the processor for all internal faults and represents the value supplied by the interrupt
controller in the case of an interrupt. Refer to Table 2-5.
2.7

Processor Exceptions

2.7.1

Access Error Exception

The exact processor response to an access error depends on the type of memory reference
being performed. For an instruction fetch, the processor postpones the error reporting until
the faulted reference is needed by an instruction for execution. Therefore, faults that occur
during instruction prefetches that are then followed by a change of instruction flow do not
generate an exception. When the processor attempts to execute an instruction with a faulted
opword and/or extension words, the access error is signaled and the instruction aborted. For
this type of exception, the programming model has not been altered by the instruction
generating the access error.
If the access error occurs on an operand read, the processor immediately aborts the current
instruction's execution and initiates exception processing. In this situation, any address
register updates attributable to the auto-addressing modes, (for example, (An)+,-(An)),
have already been performed, so the programming model contains the updated An value.
In addition, if an access error occurs during the execution of a MOVEM instruction loading
from memory, any registers already updated before the fault occurs contain the operands
from memory.
MOTOROLA
Table 2-7. Fault Status Encodings
FS[3:0]
00xx Reserved
0100 Error on instruction fetch
0101 Reserved
011x Reserved
1000 Error on operand write
1001 Attempted write to write-protected space
101x Reserved
1100 Error on operand read
1101 Reserved
111x Reserved
Chapter 2. ColdFire Core
Definition
Processor Exceptions
2-13