Bus Exception Cycles; Termination Result Summary - Motorola M-CORE MMC2001 Series Reference Manual

2.8.6 Bus Exception Cycles

The M•CORE bus interface requires assertion of TA from an external device to signal
that a bus cycle is complete. External circuitry can provide TEA when no device
responds to indicate that an error condition is associated with an access. This allows
the cycle to terminate and the processor to enter exception processing for the error
condition if appropriate.
To control termination of a bus cycle for a bus error condition properly, TA and TEA
must be asserted and negated about the same rising edge of CLK.
TA
Don't Care
Low
High
The system hardware can use the TEA signal to abort the current bus cycle when a
fault is detected. When the processor recognizes a bus error condition for an access,
the access is terminated immediately.
When a bus cycle is terminated with a bus error, the M•CORE can enter access error
exception processing immediately following the bus cycle, or it can defer processing
the exception. The instruction pre-fetch mechanism requests instruction words from
the instruction memory unit before it is ready to execute them. If a bus error occurs on
an instruction fetch, the processor does not take the exception until it attempts to use
the instruction. If an intervening instruction causes a branch or if a task switch occurs,
the access error exception for the unused access does not occur.
A bus error termination for any write or read access that references data specifically
requested by the execution unit causes the processor to begin exception processing
immediately.
MOTOROLA
2-14
Freescale Semiconductor, Inc.
Table 2-4 Termination Result Summary
TEA
Low Bus Error — terminate and take bus error exception if appropriate
High Normal cycle terminate and continue
High Insert wait states
INTEGER CPU
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Result
REFERENCE MANUAL
MMC2001