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MC9S12DT256 Device User Guide — V03.07
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to V
4. Those pins are internally clamped to V
5. This pin is clamped low to V
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Model
Human Body
Machine
Latch-up
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
1
C Human Body Model (HBM)
2
C Machine Model (MM)
3
C Charge Device Model (CDM)
Latch-up Current at T
4
C
positive
negative
Latch-up Current at T
5
C
positive
negative
92
SSPLL
, but not clamped high. This pin must be tied low in applications.
SSR
Table A-2 ESD and Latch-up Test Conditions
Description
Series Resistance
Storage Capacitance
Number of Pulse per pin
positive
negative
Series Resistance
Storage Capacitance
Number of Pulse per pin
positive
negative
Minimum input voltage limit
Maximum input voltage limit
Rating
= 125°C
A
= 27°C
A
and V
, V
and V
SSX
DDX
SSR
and V
.
DDPLL
Symbol
V
HBM
V
MM
V
CDM
I
LAT
I
LAT
or V
and V
.
DDR
SSA
DDA
Symbol
Value
R1
1500
C
100
-
-
3
3
R1
0
C
200
-
-
3
3
-2.5
7.5
Min
Max
2000
-
200
-
500
-
+100
-
-100
+200
-
-200
Unit
Ohm
pF
Ohm
pF
V
V
Unit
V
V
V
mA
mA
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