Motorola MPC533 Reference Manual page 13

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Number
10.2.4 Address and Address Space Checking........................................................... 10-5
10.2.5 Burst Support ................................................................................................. 10-5
10.2.6 Reduced Data Setup Time ............................................................................. 10-6
10.2.6.1 Case 1: Normal Setup Time....................................................................... 10-7
10.2.6.2 Case 2: Short Setup Time .......................................................................... 10-7
10.2.6.3 Summary of Short Setup Time .................................................................. 10-8
10.3 Chip-Select Timing .......................................................................................... 10-11
10.3.1 Memory Devices Interface Example ........................................................... 10-12
10.3.2 Peripheral Devices Interface Example......................................................... 10-13
10.3.3 Relaxed Timing Examples ........................................................................... 10-14
10.3.4 Extended Hold Time on Read Accesses ...................................................... 10-18
10.3.5 Summary of GPCM Timing Options........................................................... 10-22
10.4 Write and Byte Enable Signals ........................................................................ 10-24
10.5 Dual Mapping of the Internal Flash EEPROM Array ..................................... 10-25
10.6 Dual Mapping of an External Flash Region .................................................... 10-27
10.7 Global (Boot) Chip-Select Operation .............................................................. 10-27
10.8 Memory Controller External Master Support .................................................. 10-29
10.9 Programming Model ........................................................................................ 10-33
10.9.1 General Memory Controller Programming Notes ....................................... 10-33
10.9.2 Memory Controller Status Registers (MSTAT) ........................................... 10-34
10.9.3 Memory Controller Base Registers (BR0–BR3) ......................................... 10-34
10.9.4 Memory Controller Option Registers (OR0–OR3) ..................................... 10-36
10.9.5 Dual-Mapping Base Register (DMBR) ....................................................... 10-38
10.9.6 Dual-Mapping Option Register (DMOR).................................................... 10-39
11.1 General Features ................................................................................................ 11-1
11.2 Data Memory Protection Unit Features ............................................................. 11-2
11.3 L2U Block Diagram........................................................................................... 11-3
11.4 Modes Of Operation .......................................................................................... 11-3
11.4.1 Normal Mode................................................................................................. 11-3
11.4.2 Reset Operation.............................................................................................. 11-4
11.4.3 Peripheral Mode............................................................................................. 11-4
11.4.4 Factory Test Mode ......................................................................................... 11-4
11.5 Data Memory Protection.................................................................................... 11-5
11.5.1 Functional Description................................................................................... 11-5
11.5.2 Associated Registers ...................................................................................... 11-7
11.5.3 L-Bus Memory Access Violations................................................................. 11-8
11.6 Reservation Support........................................................................................... 11-8
11.6.1 Reservation Protocol...................................................................................... 11-8
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Contents
Title
Chapter 11
L-Bus to U-Bus Interface (L2U)
Contents
Page
Number
xiii