5−31 Mcbsp As Spi Master Or Slave Timing Requirements (Clkstp = 11B, Clkxp = 0); 5−32 Mcbsp As Spi Master Or Slave Switching Characteristics (Clkstp = 11B, Clkxp = 0); Mcbsp Timings As Spi Master Or Slave: Clkstp = 11B, Clkxp = 0 - Texas Instruments TMS320VC5509 Data Manual

Electrical Specifications
Table 5−31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
NO. NO.
MC33 t su(DRV-CKXH) Setup time, DR valid before CLKX high
MC34 t h(CKXH-DRV) Hold time, DR valid after CLKX high
MC25 t su(FXL-CKXH) Setup time, FSX low before CLKX high
MC26 t c(CKX) Cycle time, CLKX
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency. For example, when running parts at 144 MHz, use P = 6.94 ns. In addition to CPU frequency, the maximum operating
frequency of the serial port also depends on meeting the rest of the switching characteristics and timing requirements parameters specified.
Table 5−32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
NO. NO.
Delay time, CLKX low to FSX low ¶
MC27 t d(CKXL-FXL)
Delay time, FSX low to CLKX high #
MC28 t d(FXL-CKXH)
MC35 t d(CKXL-DXV) Delay time, CLKX low to DX valid
Disable time, DX high-impedance following last data bit from
MC30 t dis(CKXL-DXHZ)
CLKX low
MC32 t d(FXL-DXV) Delay time, FSX low to DX valid
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency. For example, when running parts at 144 MHz, use P = 6.94 ns. In addition to CPU frequency, the maximum operating
frequency of the serial port also depends on meeting the rest of the switching characteristics and timing requirements parameters specified.
§ T = CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
LSB
CLKX
FSX
DX Bit 0
DR Bit 0
Figure 5−27. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
104 SPRS163H
PARAMETER PARAMETER
MC25
MC28
MC27
MC30
MC33
MIN
MASTER §
MIN
C − 4
T − 3
−2
−1
D − 2
MC26
MSB
MC35
MC32
Bit (n−1) (n−2)
MC34
Bit (n−1) (n−2) (n−3)
‡
†
MASTER SLAVE
MAX MIN MAX
12 2 − 8P
0 2 + 8P
10
2P 16P
SLAVE
MAX MIN MAX
C + 3
T + 4
8 5P + 3 5P + 12
1 5P + 3 5P + 10
D + 7 3P + 5 3P + 14
(n−3) (n−4)
(n−4)
April 2001 − Revised January 2008
UNIT UNIT
ns
ns
ns
ns
‡
†
UNIT UNIT
ns
ns
ns
ns
ns