Multi-Master I C Bus Interface - Renesas M16C FAMILY series Hardware Manual
16-bit single-chip microcomputer
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- User manual (380 pages) ,
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- Hardware manual (468 pages)
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6
C
2 /
8
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6
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16. Multi-master I
2
The multi-master I
format, equipped with arbitration lost detection and synchronous functions. Figure 16.1 shows a block
diagram of the multi-master I
tions.
2
The multi-master I
S3D0 register, the S4D0 register, the S10 register, the S2D0 register and other control circuits.
Figures 16.2 to 16.8 show the registers associated with the multi-master I
Table 16.1 Multi-Master I
Item
Format
Communication mode
SCL clock frequency
I/O pin
2
Note 1. V
=I
C system clock
IIC
R
e
. v
2
0 .
0
J
a
. n
3
, 1
2
0
0
7
R
E
J
0
9
B
0
0
4
7
0 -
2
0
0
2 /
, 8
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1
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2 /
8
) B
2
C bus Interface
C bus interface is a serial communication circuit based on Philips I
2
C bus interface and Table 16.1 lists the multi-master I
C bus interface consists of the S0D0 register, the S00 register, the S20 register, the
2
C bus Interface Functions
Based on Philips I
7-bit addressing format
High-speed clock mode
Standard clock mode
Based on Philips I
Master transmit
Master receive
Slave transmit
Slave receive
16.1kHz to 400kHz (at V
Serial data line
Serial clock line
page 250
f o
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16. MULTI-MASTER I
2
C bus.
Function
2
C bus standard:
2
C bus standard:
IIC (1)
= 4MHz)
SDA
(SDA)
MM
SDL
(SCL)
MM
2
C bus INTERFACE
2
C bus data transfer
2
C bus interface func-
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