Watchdog Timer; Overview - Renesas H8 Series Hardware Manual

Section 9 Timers
9.6

Watchdog Timer

9.6.1

Overview

The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally.
Features
Features of the watchdog timer are given below.
• Incremented by internal clock source (φ/8192).
• A reset signal is generated when the counter overflows. The overflow period can be set from 1
to 256 times 8192/φ (from approximately 2 ms to 500 ms when φ = 4.19 MHz).
Block Diagram
Figure 9.35 shows a block diagram of the watchdog timer.
φ
Legend:
TCSRW: Timer control/status register W
TCW: Timer counter W
PSS: Prescaler S
Rev. 6.00 Sep 12, 2006 page 270 of 526
REJ09B0326-0600
φ/8192
PSS
Figure 9.35 Block Diagram of Watchdog Timer
TCSRW
TCW
Internal reset
signal