Table 310. Swj Debug Port Pins; Table 311. Flexible Swj-Dp Pin Assignment - ST STM32L4 5 Series Reference Manual

Debug support (DBG)
48.4.1 SWJ debug port pins
Five pins are used as outputs from the STM32L4x5/STM32L4x6 for the SWJ-DP as
alternate functions of general-purpose I/Os. These pins are available on all packages.
SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
NJTRST
48.4.2 Flexible SWJ-DP pin assignment
After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned
as dedicated pins immediately usable by the debugger host (note that the trace outputs are
not assigned except if explicitly programmed by the debugger host).
However, the STM32L4x5/STM32L4x6 MCUs offer the possibility of disabling some or all of
the SWJ-DP ports, and therefore the possibility of releasing the associated pins for general-
purpose I/O (GPIO) usage, except for NJTRST that can be left disconnected but cannot be
used as general purpose GPIO without loosing debugger connection. For more details on
how to disable SWJ-DP port pins, please refer to
multiplexer and
Full SWJ (JTAG-DP + SW-DP) - Reset State
Full SWJ (JTAG-DP + SW-DP) but without NJTRST
JTAG-DP disabled and SW-DP enabled
JTAG-DP disabled and SW-DP disabled
1778/1830

Table 310. SWJ debug port pins

JTAG debug port
Type Description
JTAG Test Mode
I
Selection
I JTAG Test Clock
I JTAG Test Data Input
O JTAG Test Data Output
I JTAG Test nReset
mapping.

Table 311. Flexible SWJ-DP pin assignment

Available debug ports
DocID024597 Rev 5
SW debug port
Type Debug assignment
Serial Wire Data
IO
Input/Output
I Serial Wire Clock
- -
TRACESWO if
- asynchronous trace is
enabled
- -
Section 8.3.2: I/O pin alternate function
SWJ IO pin assigned
PA13 / PA14 /
PA15 /
JTMS/ JTCK/
JTDI
SWDIO SWCLK
X X X
X X X
X X
Released
RM0351
Pin
assign
ment
PA13
PA14
PA15
PB3
PB4
PB3 / PB4/
JTDO NJTRST
X X
X