Timebase Timer Interrupt; Table 5.4-1 Register And Vector Table For Timebase Timer Interrupt - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 5 TIMEBASE TIMER
5.4

Timebase Timer Interrupt

The timebase timer can generate an interrupt request when an overflow occurs on the
specified bit of the timebase timer counter (for the interval timer function).
Interrupts for Interval Timer Function
The counter counts up on the internal count clock. When an overflow occurs on the selected
interval timer bit, the overflow interrupt request flag bit (TBTC: TBOF) is set to "1". At this time,
an interrupt request (IRQ6) to the CPU is generated if the interrupt request enable bit is enabled
(TBTC: TBIE="1"). Write "0" to the TBOF bit in the interrupt processing routine to clear the
interrupt request. The TBOF bit is set when the specified counter bit overflows, regardless of
the TBIE bit value.
Check:
When enabling an interrupt request output (TBIE = "1") after wake-up from a reset, always
clear the TBOF bit (TBOF = "0") at the same time.
Tips:
• If the TBOF bit is "1", an interrupt request is generated immediately when the TBIE bit is
changed from disabled to enabled ("0" --> "1").
• The TBOF bit is not set if the counter is cleared (TBTC: TBR = "0") at the same time as an
overflow on the specified bit occurs.
Oscillation Stabilization Delay Time and Timebase Timer Interrupt
If the interval time is set shorter than the oscillation stabilization delay time for the main clock,
an interval interrupt request from the timebase timer (TBTC: TBOF = "1") is generated at the
time when the CPU starts the main clock mode operation. In this case, disable the timebase
timer interrupt (TBTC: TBIE = "0") when changing to main-stop or subclock mode (the mode
when the main clock oscillation stops).
Register and Vector Table for Timebase Timer Interrupt

Table 5.4-1 Register and Vector Table for Timebase Timer Interrupt

Interrupt
Register
IRQ6 ILR2 (007D
Reference:
See Section 3.4.2, "Interrupt Processing" for details on the interrupt operation.
138
Interrupt level setting register
Setting bits
) L61 (Bit 5)
H
Vector table address
Upper
L60 (Bit 4) FFEE
Lower
FFEF
H H