Fujitsu MB91350A Series Manuals

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Fujitsu MB91350A Series Hardware Manual

Fujitsu MB91350A Series Hardware Manual (664 pages)

Brand: Fujitsu | Category: Microcontrollers | Size: 3.88 MB
Table of contents
Table Of Contents9................................................................................................................................................................
Chapter 1 Overview19................................................................................................................................................................
Features20................................................................................................................................................................
Block Diagram25................................................................................................................................................................
Package Dimensions27................................................................................................................................................................
Pin Layout29................................................................................................................................................................
List Of Pin Functions31................................................................................................................................................................
Input-output Circuit Forms45................................................................................................................................................................
Chapter 2 Handling The Device49................................................................................................................................................................
Precautions On Handling The Device50................................................................................................................................................................
Precautions On Using The Little-endian Area55................................................................................................................................................................
C Compiler (fcc911)56................................................................................................................................................................
Assembler (fasm911)59................................................................................................................................................................
Linker (flnk911)60................................................................................................................................................................
Debuggers (sim911, Eml911, And Mon911)61................................................................................................................................................................
Chapter 3 Cpu And Control Units63................................................................................................................................................................
Memory Space64................................................................................................................................................................
Internal Architecture67................................................................................................................................................................
Overview Of Instructions71................................................................................................................................................................
Programming Model73................................................................................................................................................................
General-purpose Registers74................................................................................................................................................................
Dedicated Registers75................................................................................................................................................................
Data Configuration82................................................................................................................................................................
Memory Map84................................................................................................................................................................
Branch Instructions85................................................................................................................................................................
Operations With A Delay Slot86................................................................................................................................................................
Operation Without Delay Slot89................................................................................................................................................................
Eit (exception, Interrupt, And Trap)90................................................................................................................................................................
Eit Interrupt Levels91................................................................................................................................................................
Icr (interrupt Control Register)93................................................................................................................................................................
Ssp (system Stack Pointer)95................................................................................................................................................................
Interrupt Stack96................................................................................................................................................................
Tbr (table Base Register)97................................................................................................................................................................
Eit Vector Table98................................................................................................................................................................
Multiple Eit Processing102................................................................................................................................................................
Operations104................................................................................................................................................................
Operating Modes108................................................................................................................................................................
Bus Modes109................................................................................................................................................................
Mode Settings110................................................................................................................................................................
Reset (device Initialization)112................................................................................................................................................................
Reset Levels113................................................................................................................................................................
Reset Sources114................................................................................................................................................................
Reset Sequence116................................................................................................................................................................
Oscillation Stabilization Wait Time117................................................................................................................................................................
Reset Operation Modes120................................................................................................................................................................
Clock Generation Control122................................................................................................................................................................
Pll Controls123................................................................................................................................................................
Oscillation Stabilization Wait Time And Pll Lock Wait Time124................................................................................................................................................................
Clock Distribution126................................................................................................................................................................
Clock Division128................................................................................................................................................................
Block Diagram Of Clock Generation Controller129................................................................................................................................................................
Register Of Clock Generation Controller130................................................................................................................................................................
Peripheral Circuits Of Clock Controller147................................................................................................................................................................
Device State Control151................................................................................................................................................................
Device States And State Transitions152................................................................................................................................................................
Low-power Consumption Modes156................................................................................................................................................................
Watch Timer161................................................................................................................................................................
Main Clock Oscillation Stabilization Wait Timer167................................................................................................................................................................
Peripheral Stop Control173................................................................................................................................................................
Chapter 4 External Bus Interface179................................................................................................................................................................
Overview Of The External Bus Interface180................................................................................................................................................................
External Bus Interface Registers185................................................................................................................................................................
Asr0 To Asr3 (area Select Register)186................................................................................................................................................................
Acr0 To Acr7 (area Configuration Registers)187................................................................................................................................................................
Awr0 To Awr3 (area Wait Register)193................................................................................................................................................................
Iowr0 To Iowr3 (i/o Wait Registers For Dmac)199................................................................................................................................................................
Chip Select Enable Register (cser)201................................................................................................................................................................
Tcr (terminal And Timing Control Register)202................................................................................................................................................................
Setting Example Of The Chip Select Area204................................................................................................................................................................
Byte Ordering (endian) And Bus Access206................................................................................................................................................................
Relationship Between Data Bus Widths And Control Signals207................................................................................................................................................................
Big Endian Bus Access208................................................................................................................................................................
Little Endian Bus Access215................................................................................................................................................................
External Access219................................................................................................................................................................
Ordinary Bus Interface223................................................................................................................................................................
Address/data Multiplex Interface233................................................................................................................................................................
Prefetch Operation236................................................................................................................................................................
Dma Access Operation240................................................................................................................................................................
Bus Arbitration246................................................................................................................................................................
Procedure For Setting A Register248................................................................................................................................................................
Chapter 5 I/o Port249................................................................................................................................................................
Overview Of The I/o Port250................................................................................................................................................................
I/o Port Registers252................................................................................................................................................................
8/16-bit Up/down Counters/timer And U-timers263................................................................................................................................................................
8/16-bit Up/down Counters/timers264................................................................................................................................................................
Overview Of 8/16-bit Up/down Counters/timers265................................................................................................................................................................
8/16-bit Up/down Counters/timer Registers270................................................................................................................................................................
Operation Of The 8/16-bit Up/down Counters/timers277................................................................................................................................................................
U-timer286................................................................................................................................................................
Overview Of The U-timer287................................................................................................................................................................
U-timer Registers288................................................................................................................................................................
Operation Of The U-timer293................................................................................................................................................................
Chapter 7 16-bit Free-running Timer And 16-bit Reload Timer296................................................................................................................................................................
16-bit Free-running Timer296................................................................................................................................................................
Structure Of The 16-bit Free-running Timer297................................................................................................................................................................
16-bit Free-running Timer Registers298................................................................................................................................................................
Operation Of The 16-bit Free-running Timer302................................................................................................................................................................
16-bit Reload Timer304................................................................................................................................................................
Structure Of The 16-bit Reload Timer305................................................................................................................................................................
16-bit Reload Timer Register307................................................................................................................................................................
Operation Of The 16-bit Reload Register310................................................................................................................................................................
Chapter 8 Programmable Pulse Generator (ppg) Timer315................................................................................................................................................................
Overview Of The Ppg Timer316................................................................................................................................................................
Ppg Timer Registers320................................................................................................................................................................
Control Status Register321................................................................................................................................................................
Ppg Cycle Setting Register (pcsr)325................................................................................................................................................................
Ppg Duty Setting Register (pdut)326................................................................................................................................................................
Ppg Timer Register (ptmr)327................................................................................................................................................................
General Control Register 10328................................................................................................................................................................
General Control Register 20331................................................................................................................................................................
Operation Of The Ppg Timer332................................................................................................................................................................
Timing Charts For Pwm Operation333................................................................................................................................................................
Timing Charts For One-shot Operation335................................................................................................................................................................
Interrupt Sources And Timing Chart (with Ppg Output Set For Ordinary Polarity)336................................................................................................................................................................
Examples Of Methods Of All-l And All-h Ppg Output337................................................................................................................................................................
Activation Of Multiple Channels Using The General Control Register338................................................................................................................................................................
Chapter 9 Interrupt Controller341................................................................................................................................................................
Overview Of The Interrupt Controller342................................................................................................................................................................
Interrupt Controller Registers346................................................................................................................................................................
Interrupt Control Register (icr)347................................................................................................................................................................
Hold Request Cancellation Request Register (hrcl)349................................................................................................................................................................
Operation Of The Interrupt Controller350................................................................................................................................................................
Chapter 10 External Interrupt And Nmi Controller359................................................................................................................................................................
Overview Of The External Interrupt And Nmi Controller360................................................................................................................................................................
External Interrupt And Nmi Controller Registers362................................................................................................................................................................
Enable Interrupt Request Register (enirn)363................................................................................................................................................................
External Interrupt Request Register (eirrn)364................................................................................................................................................................
External Level Register (elvrn)365................................................................................................................................................................
Operation Of The External Interrupt And Nmi Controller366................................................................................................................................................................
Chapter 11 Realos-related Hardware369................................................................................................................................................................
Delayed Interrupt Module370................................................................................................................................................................
Overview Of The Delayed Interrupt Module371................................................................................................................................................................
Delayed Interrupt Module Registers372................................................................................................................................................................
Operation Of The Delayed Interrupt Module373................................................................................................................................................................
Bit Search Module374................................................................................................................................................................
Overview Of The Bit Search Module375................................................................................................................................................................
Bit Search Module Registers376................................................................................................................................................................
Operation Of The Bit Search Module378................................................................................................................................................................
Chapter 12 A/d Converter381................................................................................................................................................................
Overview Of The A/d Converter382................................................................................................................................................................
A/d Converter Registers384................................................................................................................................................................
Control Status Register (adcs1)385................................................................................................................................................................
Control Status Register (adcs2)388................................................................................................................................................................
Conversion Time Setting Register (adct)391................................................................................................................................................................
Data Registers (adthx And Adtlx)393................................................................................................................................................................
Operation Of The A/d Converter394................................................................................................................................................................
Chapter 13 8-bit D/a Converter394................................................................................................................................................................
Overview Of The 8-bit D/a Converter398................................................................................................................................................................
8-bit D/a Converter Register400................................................................................................................................................................
8-bit D/a Converter Operation402................................................................................................................................................................
Chapter 14 Uart, Serial I/o Interface (sio), Input Capture Module, And Output Compare Module403................................................................................................................................................................
Uart404................................................................................................................................................................
Features Of The Uart405................................................................................................................................................................
Uart Registers408................................................................................................................................................................
Operation Of The Uart417................................................................................................................................................................
Example Of Using The Uart425................................................................................................................................................................
Serial I/o Interface (sio)428................................................................................................................................................................
Overview Of The Serial I/o Interface (sio)429................................................................................................................................................................
Serial I/o Interface Registers431................................................................................................................................................................
Operation Of The Serial I/o Interface (sio)437................................................................................................................................................................
Input Capture Module443................................................................................................................................................................
Overview Of The Input Capture Module444................................................................................................................................................................
Input Capture Module Registers446................................................................................................................................................................
Input Capture Operation448................................................................................................................................................................
Output Compare449................................................................................................................................................................
Features Of The Output Compare Module450................................................................................................................................................................
Output Compare Module Registers452................................................................................................................................................................
Operation Of The Output Compare Module455................................................................................................................................................................
Chapter 15 I 2 C Interface457................................................................................................................................................................
Overview Of The I 2 C Interface458................................................................................................................................................................
C Interface Registers462................................................................................................................................................................
Bus Status Register (ibsr)463................................................................................................................................................................
Bus Control Register (ibcr)466................................................................................................................................................................
Clock Control Register (iccr)473................................................................................................................................................................
10-bit Slave Address Register (itba)475................................................................................................................................................................
10-bit Slave Address Mask Register (itmk)476................................................................................................................................................................
7-bit Slave Address Register (isba)478................................................................................................................................................................
7-bit Slave Address Mask Register (ismk)479................................................................................................................................................................
Data Register (idar)480................................................................................................................................................................
Clock Disable Register (idbl)481................................................................................................................................................................
Explanation Of I 2 C Interface Operation482................................................................................................................................................................
Operation Flowcharts486................................................................................................................................................................
Chapter 16 Dma Controller (dmac)489................................................................................................................................................................
Overview490................................................................................................................................................................
Detailed Explanation Of Registers493................................................................................................................................................................
Dmac Ch0 To Ch4 Control/status Registers A494................................................................................................................................................................
Dmac Ch0 To Ch4 Control/status Registers B500................................................................................................................................................................
Dmac Ch0 To Ch4 Transfer Source/transfer Destination Address Setting Registers506................................................................................................................................................................
Dmac Ch0 To Ch4 Dmac All-channel Control Register508................................................................................................................................................................
Explanation Of Operation510................................................................................................................................................................
Overview Of Operation511................................................................................................................................................................
Setting A Transfer Request514................................................................................................................................................................
Transfer Sequence515................................................................................................................................................................
General Aspects Of Dma Transfer519................................................................................................................................................................
Addressing Mode521................................................................................................................................................................
Data Types522................................................................................................................................................................
Transfer Count Control523................................................................................................................................................................
Cpu Control524................................................................................................................................................................
Hold Arbitration525................................................................................................................................................................
Operation From Starting To End/stopping526................................................................................................................................................................
Transfer Request Acceptance And Transfer527................................................................................................................................................................
Clearing Peripheral Interrupts By Dma528................................................................................................................................................................
Temporary Stopping529................................................................................................................................................................
Operation End/stopping530................................................................................................................................................................
Stopping Due To An Error531................................................................................................................................................................
Dmac Interrupt Control532................................................................................................................................................................
Dma Transfer During Sleep533................................................................................................................................................................
Channel Selection And Control534................................................................................................................................................................
Supplement On External Pin And Internal Operation Timing536................................................................................................................................................................
Data Path543................................................................................................................................................................
Dma External Interface547................................................................................................................................................................
Chapter 17 Flash Memory551................................................................................................................................................................
Outline Of Flash Memory552................................................................................................................................................................
Flash Memory Registers557................................................................................................................................................................
Flash Control/status Register (flcr) (cpu Mode)558................................................................................................................................................................
Flash Memory Wait Register (flwc)561................................................................................................................................................................
Explanation Of Flash Memory Operation563................................................................................................................................................................
Automatic Algorithm Of Flash Memory565................................................................................................................................................................
Command Sequence566................................................................................................................................................................
Checking The Automatic Algorithm Operating Status570................................................................................................................................................................
Writing To And Erasing Flash Memory575................................................................................................................................................................
Read/reset Status576................................................................................................................................................................
Data Writing577................................................................................................................................................................
Data Erasure (chip Erasure)579................................................................................................................................................................
Data Erasure (sector Erasure)580................................................................................................................................................................
Temporary Sector Erase Stop582................................................................................................................................................................
Sector Erase Restart583................................................................................................................................................................
Chapter 18 Mb91f355a/f353a/f356b/f357b Serial Programming Connection586................................................................................................................................................................
Basic Configuration Of Mb91f355a/f353a/f356b/f357b Serial Programming Connection586................................................................................................................................................................
Pins Used For Fujitsu Standard Serial Onboard Writing587................................................................................................................................................................
Examples Of Serial Programming Connection588................................................................................................................................................................
System Configuration Of Flash Microcontroller Programmer590................................................................................................................................................................
Other Precautionary Information591................................................................................................................................................................
Access Restriction Functions593................................................................................................................................................................
Chapter 19 Data Internal Ram/instruction Internal Ram594................................................................................................................................................................
Explanation Of Registers595................................................................................................................................................................
Appendix599................................................................................................................................................................
Appendix A I/o Map600................................................................................................................................................................
Appendix B Interrupt Vector612................................................................................................................................................................
Appendix C Pin States In Each Cpu State615................................................................................................................................................................
Appendix D Instruction Lists621................................................................................................................................................................
Index637................................................................................................................................................................

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